FBCs are simple and attractive in terms of scaling over conventional dynamic random-access memory (DRAM) because of the FBCs' capacitor-less structure. FBCs make use of a floating body to store data in the form of a floating body potential. For example, the value 1 is achieved in FBCs when a positive voltage is applied to a bitline (BL) to initialize impact ionization, and holes are accumulated in the body that raise the body potential. The value 0 is achieved when a negative voltage is applied to the BL, and holes are extracted from the body and reduce the body potential. Despite the foregoing, FBCs still experience issues associated with DRAM, such as refresh procedures to replenish the charge lost during read or after prolonged use. Additionally, limited data storage capacity in FBCs exacerbates the refresh rate issue.
A need therefore exists for methodology enabling formation of improved FBCs with faster programming and lower refresh rates, and the resulting device.